1. Field of the Invention
This invention relates to analysis of electronic circuits under various conditions, and more particularly, a system and method for analyzing the effects of simultaneous switch noise (SSN) in electronic systems.
2. Description of the Relevant Art
As the density of integrated circuits increases, the problems associated with signal switching noise become greater. Many integrated circuits have a large number of input/output (I/O) drivers. Several hundred drivers may be present in some integrated circuits, and this number will undoubtedly become larger as packaging density increases in the future. Noise that occurs in an electronic system when a large number of drivers simultaneously switch from one state to another is known as simultaneous switch noise (SSN). The problem may be even more acute when the drivers all switch in the same direction (e.g. high to low). When a large number of drivers switch simultaneously, various signal integrity problems may occur. For example, SSN may result in erroneous noise pulses on signal lines, and may also alter system timing. SSN from a given chip may cause receivers of other chips in an electronic system, or receivers on the same chip, to receive incorrect results. SSN may in some cases also lead to power supply fluctuations severe enough to cause damage to the circuits comprising the load, or even internal damage to the power supply itself.
Software tools for analyzing the effects of SSN have been developed. The majority of these tools approach the SSN problem as an inductance issue. In order to analyze SSN as an inductance problem may require a number of coupled inductance matrices. Each of these matrices may include a large number of inductive elements. Due to the large number of elements, simulations involving these matrices may consume a large amount of computational resources, and have very long compute times.
It should also be noted that advanced packaging techniques have reduced the inductive aspect of the SSN problem. Many newer integrated circuit packages have their own power and ground planes. Signal traces in such packages tend to behave more like transmission lines, having distributed parameters such as impedance and delay instead of lumped parameters, such as inductance. Many packages, such as ball-grid array packages, replace traditional lead structures with solder balls that connect to a printed circuit board, further reducing inductance. In some cases, a signal path in such a package may have less than 1% of the inductance of a similar signal path in a traditional lead-frame package (e.g. a quad flat-pack with gull-wing leads).
Many prior art SSN analysis techniques fail to account for skin effect, wherein alternating current signals travel on or near the surface of a solid plane or conductor. Skin depth decreases in a manner inversely proportional to the frequency of a signal traveling on a plane or conductor. For example, at 10 kHz, the skin depth of copper is 0.66 mm, while at 100 MHz, the skin depth of copper is 0.0066 mm. Many prior art techniques treat the signal as traveling within the conductor, which may lead to a faulty analysis of the SSN problem, as it may incorrectly model current flow within the system.
Another problem with prior art SSN analysis techniques is the modeling of the attachment of a silicon driver. A silicon driver in an integrated circuit typically includes three terminals, and must be coupled to a voltage supply plane, a ground (or reference) plane, and a transmission line which carries the signal. Many prior art systems connect the voltage supply plane in series with an impedance representing a transmission line to arrive at a superimposed analysis solution for both the transmission line and the voltage supply plane. By connecting the transmission line impedance in series with the voltage supply plane, such techniques may fail to account for all of the current flowing through the driver. At best, this technique leads to an incomplete solution of the SSN analysis.
Still another problem with prior art SSN analysis techniques is the use of ideal power supplies in the simulation. An ideal power supply is a power supply that has zero output impedance. In reality, such power supplies do not exist. An ideal power supply may be configured to provide a constant voltage between its terminals regardless of the behavior of the load circuit. Thus, such analysis techniques employing ideal power supplies may fail to account for power supply fluctuations that may occur due to the simultaneous switching of a large number of drivers.
With the problems mentioned above, it has become increasingly difficult to get accurate results to simulations of the SSN problem. Often times, results from a simulation and analysis will not have any meaningful correlation to the SSN problem of hardware that is built based on such analysis. In part due to the lowered inductance associated with advanced packaging techniques, as well as the higher frequencies and number of drivers present, the SSN problem may often times be more of a plane bounce problem than an inductance problem, as it is often thought of traditionally. Thus, a different approach is necessary in order to better understand the SSN problem, and thus design hardware that effectively addresses the problem.
The problems outlined above are in large part solved by a system and method for simultaneous switch noise (SSN) analysis of electronic circuits. In one embodiment, a model may be provided for the electronic circuit to be analyzed. The electronic circuit may be an integrated circuit, a multi-chip module, a printed circuit assembly, or other type, and may in some embodiments include combinations of these types. The electronic circuit may include a plurality of drivers, each of which may be coupled to a power plane, a ground plane, and a transmission line. The connection of the driver may be accurately modeled in this manner. Each driver may be configured to switch between a logic high voltage and a logic low voltage. The modeled electronic circuit may also include a voltage source coupled to the power plane and the ground plane, a voltage regulator module, and a plurality of decoupling capacitors. The simultaneous switching of a plurality of drivers, from a logic high to a logic low, or vice versa, may be simulated. The system and method may then allow for the calculation of solutions for the transmission line and the power planes (as will be detailed below). The transmission line solution and power plane solution may be superimposed on each other, which may allow for an analysis of plane bounce, which may include one or more fluctuations in the voltage between the power plane and the ground planes.
In one embodiment, the model of an electronic circuit to be analyzed for SSN may be a mathematical model, such as a SPICE model, which may be simulated on a computer system. The model of the circuit may include a variety of components present in the circuit, including (but not limited to) resistors, capacitors, inductors, power supplies, integrated circuits, and a voltage regulator module. The power and ground planes may be modeled as a mesh of transmission lines. The model may also include a plurality of drivers configured to switch between two different logic voltage levels. The system and method for SSN analysis may be configured to simulate the simultaneous switching of a large number of these drivers from one logic voltage to the other. In some embodiments, transmission lines may be terminated with an open circuit, while in others, transmission lines may be terminated using resistors.
In one embodiment, a transmission line solution may be obtained from analysis of voltage waves and current waves propagating from each driver. A first voltage wave and a first current wave may propagate from the drivers involved in the simultaneous switching to a power plane in the circuit. A second voltage wave and a second current wave may propagate from the drivers to a ground plane. A power plane solution may be obtained by analyzing electrical charge accumulating on both the power and ground planes of the circuit, as well as a third voltage wave and a third current wave propagating radially from each driver. The transmission line solution may be superimposed with the power plane solution in order to produce a final solution. A final solution may include an analysis of plane bounce as described above.
The SSN analysis may be affected by the arrangement of transmission lines with respect to the power and ground planes in various embodiments. In one embodiment of an electronic circuit, transmission lines may be arranged above a power plane, which may in turn be arranged above a ground plane. In other embodiments, transmission lines may be arranged between the power plane and ground plane. Some embodiments may also include multiple power and ground planes stacked on top of one another, with transmission lines arranged above, below, or between the various layers of power and ground planes. When transmission lines are arranged between a power and ground plane, transmission line solutions may be calculated by modeling each transmission line as two independent transmission lines, obtaining and independent solution for each independently modeled transmission line, and superimposing their solutions upon one another.
Thus, in various embodiments, the system and method described herein may allow for a more accurate analysis of the SSN problem. In particular, plane bounce may be more accurately analyzed. The system and method for SSN analysis may be used in conjunction with other circuit design tools. For example, the system and method for SSN analysis may be used in conjunction with design tools for determining decoupling capacitors in an electronic circuit. Furthermore, by analyzing the problem as a plane bounce problem, many of the inductances and mutual inductances that were accounted for during traditional SSN analysis methods may be eliminated from the analysis of the method described herein. This may result in a significant reduction in computation time.